This application relies for priority upon Korean Patent Application No. 2000-00940, filed on Jan. 10, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device, and more particularly to an arrangement of input/output lines and a circuit associated with sense amplifiers in a semiconductor memory device.
A general arrangement of a semiconductor memory device, as shown in FIG. 1, includes a divided array of memory banks and a peripheral circuit. Assuming that the semiconductor memory device formed on semiconductor chip 1 has a storage capacity of 128 Mb, four banks BANK1xcx9cBANK4 each has a capacity of 32 Mb. The peripheral circuit disposed between the memory banks at the vertical center of the chip 1 includes circuits for decoding, buffering, and data input/output.
In constructing a 32 MB memory bank, as shown in FIG. 2, a row decoder 20 and column decoder 30 are positioned on the sides of the memory bank. 8K (K is 210) wordlines (IWL) and 4K bitline (BL) pairs are arranged in a matrix form. The memory array of 32 Mb in the memory bank is divided into sixteen memory blocks 40 (designated also MB0xcx9cMB15) along a row direction. Each of these memory blocks has a storage capacity of 2 Mb with 512 wordlines and 4K bitlines. 1K (1024) column selection lines CSL0xcx9cCSL1023 extending from the column decoder 30 are arranged on and over the memory array, with each column selection line corresponding to four bitlines.
For a given cycle, two wordlines for each memory bank are activated. For example, the row decoder 20 selects one memory block (e.g., MB1) among the memory blocks MB0xcx9cMB7 and one memory block (e.g., MB9) among the memory blocks MB8xcx9cMB15, and then selects one wordline in each of the selected memory blocks MB1 and MB9. Namely, two wordlines (WL) are selected when one memory bank is selected, and other memory blocks in the selected memory bank are non-selected.
FIG. 3 shows the section A in dashed outline of FIG. 2, including the upper half of memory block MB1 and surrounding circuitry. Between adjacent memory blocks, a sense amplifier block is positioned. For instance, sense amplifier blocks SABLK0 and SABLK1 are interposed between the memory blocks MB0 and MB1, and between the memory blocks MB1 and MB2, respectively. The sense amplifier block comprises bitline isolation regions 50 and 60, bitline precharging/equalizing region 70, P-channel sense amplifier region 80, N-channel sense amplifier region 90, and input/output gating region 100 (in dashed outline). See U.S. Pat. No. 5,761,123 entitled SENSE AMPLIFIER CIRCUIT OF A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, relevant to circuit elements provided to the bitline isolation regions, the precharging/equalizing region, and the sense amplifier regions.
In the input/output gating region 100, four complementary pairs of input/output lines, IOi, /IOi, IOj, /IOj, IOk, /IOk, IOl, and /IOl, are arranged perpendicular to the bitlines, and column selection gates GT are connected between bitline pairs and input/output line pairs. When a row of the memory block MB1 is selected by the row decoder 20 and a column selection line (e.g., CSL0) is selected by the column decoder 30, bitline pair BL0 and /BL0 is connected to the input/output line pair IOi and /IOi located on the left side of MB1, through the corresponding column selection gate pair whose gates are coupled to CSL0. Also, BL2 and /BL2 are connected to IOj and /IOj arranged at the left side of MB1, through their corresponding column selection gates whose gates are also coupled to CSL0.
At the same time, BL1 and /BL1 are connected to IOi and /IOi arranged at the right side of MB1, and BL3 and /BL3 are connected to IOj and /IOj arranged at the right side of MB1, through their corresponding column selection gates whose gates are coupled to CSL0. Thus, one of the column selection lines can connect four bitline pairs to four input/output line pairs alternately arranged on the either side of the memory block MB1. Since two wordlines (WL signals corresponding to MB1, MB9) are activated upon the selection of one memory bank, data of four bits for each wordline are transferred to four corresponding input/output line pairs. As a result, eight bits are normally read out from one selected memory bank, in keeping with an 8-bit data structure.
If two column selection lines (e.g., CSL0 and CSL512) are selected at the same time, 8-bit data are read out from the selected memory block MB1 by the sense amplifier block corresponding thereto. In more detail, when CSL0 is selected, four bitline pairs BL0, /BL0, BL1, /BL1, BL2, /BL2, BL3, and /BL3 are connected to their corresponding input/output lines IOi, /IOi, IOj, and /IOj. In the same manner, the bitline pairs of BL2048 and /BL2048, and of BL2050 and /BL2050, are connected to the input/output line pairs of IOk and /IOk, and of IOl and /IOl, respectively, the input/output line pairs being arranged at the left side of MB1, through their corresponding column selection gate GT whose gates are coupled to CSL512. And the bitline pairs of BL2049 and /BL2049, and of BL2051 and /BL2051, are connected to the input/output line pairs of IOk and /IOk, and of IOl and /IOl, respectively, the input/output line pairs being arranged at the right side of MB1, through their corresponding column selection gate GT whose gates are coupled to CSL512.
Therefore, it can be seen from FIG. 3 that eight bitline pairs are each connected to eight input/output line pairs alternately arranged on either side of the selected memory block MB1 when two column selection lines (e.g., CSL0 and CSL512) are activated at the same time. Since two wordlines are selected in a given memory bank, activation of two column selection signals enables 16-bit data to be read out of the selected memory banks.
It is possible to alternate between the 8-bit and 16-bit data read-out pattern in the array architecture shown in FIG. 3. It is also possible to construct a 4-bit data structure by multiplexing the input/output line pairs with additional column address bits. Other bitlines and selection gates involved in the activation of other column selection lines are operationally arranged in the same configuration as described above. FIG. 4 shows a layout pattern of the circuit arrangement of FIG. 3, wherein plural gate lines 102 made of polysilicon layers are formed over plural N+ active regions 101. The plural bitlines and the plural active regions 101 are connected at plural contact regions 11, and the active regions and input/output lines made of a metal or conductive material are connected at plural contact regions 13.
The width of the input/output gating region, L, is determined by an integration density dependent upon the number of input/output lines disposed therein. In the gating region interposed between the adjacent memory blocks, eight input/output lines are arranged to provide an efficient data access operation, alternately positioned on either side of a memory block. However, a chip size of a memory device becomes even smaller as the size of electronic apparatus employing the memory device becomes smaller. The density of a memory device, which must is increase, is greatly influenced by repetitive patterns of the signal lines such as bitlines and input/output lines. As may be seen from FIG. 4, the regular horizontal arrangement of the eight input/output lines within a given sense amplifier block leaves inoperable regions thereof having no contacts to the active regions. This causes the width L to be unnecessarily and undesirably extended. Accordingly, there is a need for a more efficient input/output line arrangement.
It is therefore an object of the present invention to provide an efficient input/output line arrangement that is advantageous in reducing the size (area) of a semiconductor memory device.
It is another object of the invention to provide an optimized input/output line structure in a semiconductor memory device by reducing the circuit area occupied by a repetitive or otherwise wasteful arrangement of the input/output lines.
In order to attain the above objects, a semiconductor memory device includes a plurality of memory blocks, and a plurality of input/output lines associated with the memory blocks, the input/output lines being divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between adjacent memory blocks while first portions of the input/output lines of the second group are arranged in circuit blocks around the adjacent memory blocks, and second portions of the input/output lines of the first group are arranged in circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks. The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and the scope of the invention will be defined by the appended claims.